PLDs may be used to implement large systems that include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing design, routing connections between components on the PLD utilizing available routing resources can be among the most challenging and time consuming. The complexity of large systems often requires the use of EDA tools to manage and optimize their design onto physical target devices. Automated routing algorithms in EDA tools perform the time-consuming task of routing connections between components on the physical devices.
Standard automated routing algorithms available in off the shelf EDA tools may be incapable of routing connections between components on the PLD with the available routing resources on the PLD. Alternatively, standard algorithms may be unable to route some connections such that the connections are fast enough to meet the design performance target. In some instances, manual routing techniques are more efficient in identifying routing strategies that automated algorithms are slow to or even sometimes unable to identify. Some EDA tools allow users to manually select routing resources for making connections. Many of these EDA tools, however, require that the user identify the specific routing resources for making the connections. Many of these EDA tools also require that once the user wishes to specify a routing resource to be used for making one connection that the user specify each and every routing resource to be used for making all the connections constituting a given signal, or even all the connections in the entire design. Although these options may offer the user some flexibility, the EDA tools require the user to input a large amount of information which may be time-consuming and subject to inputting errors.
Thus, what is needed is an efficient and effective method and apparatus for allowing user-specified routing constraints to be specified and enforced.